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Volumn 2003-January, Issue , 2003, Pages 236-241

Fault diagnosis for physical defects of unknown behaviors

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTS; ELECTRIC FAULT CURRENTS; FAILURE ANALYSIS;

EID: 16244394347     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2003.1250816     Document Type: Conference Paper
Times cited : (9)

References (10)
  • 2
  • 4
    • 0030383964 scopus 로고    scopus 로고
    • Beyond the Byzantine Generals: Unexpected Behavior and Bridging Fault Diagnosis
    • D. Lavo, T. Larrabee, and B. Chess, "Beyond the Byzantine Generals: Unexpected Behavior and Bridging Fault Diagnosis", Proc. Intl. Test Conf., pp. 611-619, 1996.
    • (1996) Proc. Intl. Test Conf. , pp. 611-619
    • Lavo, D.1    Larrabee, T.2    Chess, B.3
  • 5
    • 0034478411 scopus 로고    scopus 로고
    • Precise Test Generation for Resistive Bridging Fault of CMOS Combinational Circuits
    • T. Maeda and K. Kinoshita, "Precise Test Generation for Resistive Bridging Fault of CMOS Combinational Circuits", Proc. Intl. Test Conf., pp. 510-519, 2000.
    • (2000) Proc. Intl. Test Conf. , pp. 510-519
    • Maeda, T.1    Kinoshita, K.2
  • 7
    • 0025535896 scopus 로고
    • QUIETEST: A Quiescent Current Testing Methodology for Detecting Short Faults
    • Nov.
    • W. Mao and R. K. Gulati, "QUIETEST: A Quiescent Current Testing Methodology for Detecting Short Faults", Proc. ICCAD'90, pp. 280-283, Nov. 1990.
    • (1990) Proc. ICCAD'90 , pp. 280-283
    • Mao, W.1    Gulati, R.K.2
  • 8
    • 0027883887 scopus 로고
    • Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds
    • P. Maxwell and R. Aiken, "Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds", Proc. Intl. Test Conf., pp. 63-72, 1993.
    • (1993) Proc. Intl. Test Conf. , pp. 63-72
    • Maxwell, P.1    Aiken, R.2
  • 10
    • 84948442818 scopus 로고    scopus 로고
    • Speeding Up the Byzantine Fault Diagnosis Using Symbolic Simulation
    • 111
    • S. Huang, "Speeding Up the Byzantine Fault Diagnosis Using Symbolic Simulation", Proc. VLSI Test Symp., pp. 111-111,-2002.
    • (2002) Proc. VLSI Test Symp. , pp. 111
    • Huang, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.