Simulation-based diagnosis for crosstalk faults in sequential circuits

Proceedings of the Asian Test Symposium

Volumn , Issue , 2001, Pages 63-68

  Takahashi, Hiroshi ^a   Phadoongsidhi, Marong ^b   Higami, Yoshinobu ^a   Saluja, Kewal K ^b   Takamatsu, Yuzo ^a  

^a EHIME UNIVERSITY   (Japan)

^b University of Wisconsin Madison   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CALCULATIONS; COMPUTER SIMULATION; CROSSTALK; FLIP FLOP CIRCUITS; RESPONSE TIME (COMPUTER SYSTEMS); SEQUENTIAL CIRCUITS;

CENTRAL PROCESSING UNIT TIME; CROSSTALK FAULT SIMULATION; CROSSTALK-INDUCED PULSE FAULTS;

INTEGRATED CIRCUIT TESTING;

EID: 0035701291     PISSN: 10817735     EISSN: None     Source Type: Journal    
DOI: 10.1109/ATS.2001.990260     Document Type: Article

References (7)

1. Analytic method for crosstalk delay and pulse analysis under non-ideal inputs
2. Test generation in VLSI circuits for crosstalk noise
3. Test generation for crosstalk-induced delay in integrated circuits
4. Test generation for crosstalk-induced delay faults: Framework and computational results
5. A fault simulator method for crosstalk faults in synchronous sequential circuits
6. On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits
7. An efficient algorithm for sequential circuit test generation