Fault simulation method for crosstalk faults in synchronous sequential circuits

Proceedings - Annual International Conference on Fault-Tolerant Computing

Volumn , Issue , 1996, Pages 38-43

  Itazaki, Noriyoshi ^a   Idomoto, Yasutaka ^a   Kinoshita, Kozo ^a  

^a OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CROSSTALK; ELECTRIC NETWORK ANALYSIS; EQUIVALENT CIRCUITS; FAULT TOLERANT COMPUTER SYSTEMS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT TESTING; LOGIC GATES; MATHEMATICAL MODELS; MINIMIZATION OF SWITCHING NETS; VECTORS; VLSI CIRCUITS;

CLOCK LINES; SYNCHRONOUS SEQUENTIAL CIRCUITS;

SEQUENTIAL CIRCUITS;

EID: 0029715011     PISSN: 07313071     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)