A 6.7-fF/μm2 bias-independent gate capacitor (BIGCAP) with digital CMOS process and its application to the loop filter of a differential PLL

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 3, 2005, Pages 719-725

  Takamiya, Makoto ^a   Mizuno, Masayuki ^a  

^a NEC CORPORATION   (Japan)

Author keywords

Bias dependence; Differential; Gate capacitor; Loop filter; Phase locked loop (PLL)

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ELECTRODES; ELECTRONS; MIM DEVICES; PHASE LOCKED LOOPS; RADIO SYSTEMS; WAVE FILTERS;

BIAS DEPENDENCE; DIFFERENTIAL; GATE CAPACITORS; LOOP FILTERS;

CAPACITORS;

EID: 16244373402     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.843620     Document Type: Conference Paper

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