Electrical Characterization of Circuits with Low K Dielectric Films and Copper Interconnects

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Volumn , Issue , 2001, Pages 217-224

  Kane, Terence ^a   McGinnis, Patrick ^a   Engel, Brett ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER INTERCONNECTS; FLUORINATED SILICON GLASS (FSG); FOCUSED ION BEAMS (FIB);

ATOMIC FORCE MICROSCOPY; CAPACITANCE; COPPER; DIELECTRIC FILMS; MICROPROCESSOR CHIPS; NETWORKS (CIRCUITS); PIEZOELECTRIC DEVICES; POLISHING; POROSITY; REACTIVE ION ETCHING; SILICON ON INSULATOR TECHNOLOGY;

OPTICAL INTERCONNECTS;

EID: 1542270709     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

1. E. Leobandung et al., "High Performance 0.18μm SOI CMOS Technology," IEEE International Electron Devices Meeting Technical Digest, 1999: 679-682
2. P. Smeys et al., "A High Performance 0.13μm SOI CMOS Technology with Cu Interconnects and low-k BEOL Dielectric," Symposium on VLSI Technology Digest of Technical Papers, 2000: 184-185
3. J. Thong, Electron Beam Testing Technology, Plenum Press, New York (1993)
4. G. Binnig, C.F. Quate, and Ch. Gerber, Phys. Rev. Lett., 56, 930 (1986)
5. G. Binnig, and D.P.E. Smith, Rev. Sci. Instrum, 57, 1688 (1986)
6. K. Krieg, Richard Qi, Douglas Thomson, Greg Bridges, "Electrical Probing and Surface Imaging of Deep Sub-Micron Integrated Circuits, "99" ISTFA Proceedings, pp. 39-45 (1999).
7. Kenneth Krieg, Douglas Thomson, Greg Bridges, "Electrical Probing of Deep Sub-Micron Integrated Circuits Using Scanning Probe Techniques", Supplement I to EDFAS Failure Analysis Desk Reference, version 4, November 11, 2001.
8. T.Kikkawa, "Current and Future Low-k Dielectrics for Copper Interconnects," IEEE IEDM Proceedings., Dec. 2000
9. K. Kinoshita et. al., "Process Design Methodology for Via-Shape-Controlled Copper Dual-Damascene Interconnects in Low-k Organic Film," IEEE IEDM Proceedings., Dec. 2000
10. L. Peters, "Ramping The 0.13μm Generation," Semiconductor International, January 2001, pp. 57-68
11. F. Assaderaghi, et.al. al., "A 7.9/5.5 psec. Room/Low Temperature SOI CMOS", Proceedings of IEDM '97', pp. 415-418 (1997).
12. J. Gautier, et.al. al., "SOI Floating Body, Device and Circuit Issues" Proceedings of IEDM '97', pp. 407-410 (1997).
13. T. Fuse, et. al., "0.5V SOI CMOS Pass-Gate Logic", '96' IEEE International Solid State Circuits Conference, pp. 88-89 (1996).
14. C. Chuang, et. al., "SOI for Digital CMOS VLSI", Proceedings of IEEE, vol. 86, no.4, pp. 689-720 (1998).
15. th" ISTFA Proceedings, pp. 327-329 (2000).
16. ISTFA® 2000 Book and CD-ROM Set, proceedings of the 26th International Symposium for Testing and Failure Analysis; ASM International, Materials Park, OH 44073-0002, figure 14, page 404"
17. th " ISTFA Proceedings, pp. 397-405 (2000).