A 110nm 512Mb DDR DRAM with vertical transistor trench cell

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 114-115

  Wuensche, S ^a   Jacunski, M ^b   Streif, H ^a   Sturm, A ^a   Morrish, J ^b   Roberge, M ^b   Clark, M ^b   Nostrand, T ^b   Stahl, E ^a   Lewis, S ^b   Heath, J ^a   Wood, M ^b   Vogelsang, T ^a   Thoma, E ^b   Gabric, J ^b   Kleiner, M ^a   Killian, M ^a   Poechmueller, P ^a   Mueller, W ^a   Bronner, G ^b  

^a INFINEON TECHNOLOGIES   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CHIP SCALE PACKAGES; FIELD EFFECT TRANSISTORS; GATES (TRANSISTOR); SEMICONDUCTOR DEVICE STRUCTURES; STATIC RANDOM ACCESS STORAGE;

DOUBLE GATE VERTICAL PASS TRANSISTOR; STATIC DYNAMIC RANDOM ACCESS STORAGE; VERTICAL TRANSISTOR TRENCH CELL;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0242695792     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. T. Kirihata, et al, "A 113mm2 600Mb/s/pin 512Mb DDR2 SDRAM with vertically-folded bitline architecture", ISSCC, pp. 382-383, February 2001.
2. 2 DRAM cell with a double gate vertical transistor device for 100nm and beyond", IEDM, pp. 415-418, December 2001.