A hybrid CMOS-SET co-fabrication platform using nano-grain polysilicon wires

Microelectronic Engineering

Volumn 78-79, Issue 1-4, 2005, Pages 239-243

  Ecoffey, S ^a   Pott, V ^a   Mahapatra, S ^a   Bouvet, D ^a   Fazan, P ^a   Ionescu, A M ^a  

^a EPFL   (Switzerland)

Author keywords

"Hot" ion implantation; Hybrid CMOS SET co fabrication; Ultra thin polysilicon

Indexed keywords

DEPOSITION; DIFFUSION; GRAIN SIZE AND SHAPE; HYSTERESIS; ION IMPLANTATION; MOSFET DEVICES; NANOSTRUCTURED MATERIALS; POLYSILICON; SCANNING ELECTRON MICROSCOPY;

ELECTRON TRANSISTORS; HOT ION IMPLANTATION; HYBRID CMOS-SET CO-FABRICATION; ULTRA-THIN POLYSILICON;

CMOS INTEGRATED CIRCUITS;

EID: 14944341776     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2004.12.033     Document Type: Conference Paper

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