Ultra-low-voltage robust design issues in deep-submicron CMOS

Conference Proceedings - 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004

Volumn , Issue , 2004, Pages 49-52

  Vladimirescu, Andrei ^a,b   Cao, Yu ^a   Thomas, Olivier ^b   Qin, Huifang ^a   Markovic, Dejan ^a   Valentian, Alexandre ^b   Ionita, Razvan ^b   Rabaey, Jan ^a   Amara, Amara ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Institut Superieur d'Electronique de Paris   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DATA RETENTION VOLTAGE (DRV); STATIC-NOISE MARGIN (SNM); SYSTEM-ON-A-CHIP (SOC) INTEGRATION; VOLTAGE TRANSFER CURVES (VTC);

ELECTRIC POTENTIAL; LEAKAGE CURRENTS; LOGIC DESIGN; MATHEMATICAL MODELS; MOS CAPACITORS; MOSFET DEVICES; PERSONAL DIGITAL ASSISTANTS; STATISTICAL METHODS; TRANSISTORS;

CMOS INTEGRATED CIRCUITS;

EID: 14844303791     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. J. Rabaey et al, "PicoRadios for Wireless Sensor Networks: The Next Challenge in Ultra-Low-Power Design," Proc. of ISSCC, pp. 200-201, San Francisco, Feb 2002.
2. O. Thomas, A. Valentian, A. Vladimirescu, and A. Amara, "An Accurate Estimation Model for Subthreshold CMOS SOI Logic", Proc. ESSCIRC, pp. 275-279, Florence, Italy, Sep 2002.
3. S.R. Nassif, "Design for variability in DSM technologies," ISQED 2000, pp. 451-454, 2000.
4. Y. Cao, H. Qin, R. Wang, P. Friedberg, A. Vladimirescu, and J. Rabaey, "Yield Optimization with Energy-Delay Constraints in Low-Power Digital Circuits," Proc. EDSSC, pp. 285-288, Hong Kong, Dec. 2003.
5. H. Qin, Y. Cao, D. Markovic, A. Vladimirescu, and J. Rabaey, "SRAM Leakage Suppression by Minimizing Standby Supply Voltage," ISQED 2004, pp. 451-454, Mar. 2004.
6. O. Thomas, A. Amara, and A. Vladimirescu, "Stability Analysis of a 400 mV 4-Transistor CMOS-SOI SRAM Cell Operated in Subthreshold." Proc. EDSSC, pp. 247-250, Hong Kong, Dec. 2003.
7. O. Thomas, and A. Amara, "An SOI 4 Transistors Self-Refresh Ultra-Low-Voltage memory cell", ISCAS, May 2003, Thailand, Bangkok.
8. Y. Nakagome, M. Horiguchi, T. Kawahara, and, K. Itoh, "Review and future prospects of low-voltage RAM circuits," IBM J. Res & Dev., Vol. 47, No. 5/6, pp. 525-552, Sep/Oct 2003.