Stability analysis of a 400 mV 4-transistor CMOS-SOI SRAM cell operated in subthreshold

2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

Volumn , Issue , 2003, Pages 247-250

  Thomas, Olivier ^a   Amara, Amara ^a   Vladimirescu, Andrei ^b  

^a ISEP   (France)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELLS; CYTOLOGY; ELECTRON DEVICES; SEMICONDUCTOR STORAGE; SOLID STATE DEVICES;

ANALYTICAL APPROACH; DESIGN ROBUSTNESS; ESTIMATION MODELS; MEMORY CELL; STABILITY ANALYSIS; STABILITY PROBLEM; SUBTHRESHOLD; ULTRA-LOW-VOLTAGE;

STATIC RANDOM ACCESS STORAGE;

EID: 14844331919     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EDSSC.2003.1283524     Document Type: Conference Paper

References (11)

1. E. Vittoz and J. Fellrath, "CMOS analog integrated circuits based on weak inversion operation," IEEE J. Solid-State Circuits, vol. SC-12, pp. 224-231, Jun 1977.
2. hendrawan Soeleman and Kaushik Roy, "Ultra-Low Power Digital Subthreshold Logic Circuit, ISLPED, Aug 1999, USA, San Diego.
3. hendrawan Soeleman and Kaushik Roy, "Robust Ultra-Low Power Subthreshold DTMOS Logic, ISLPED, Aug 2000, Italy, Rapallo.
4. Akihiro Ebina, "Ultra-low power CMOS IC using partially depleted SOI technologies.", EPSON, SOI workshop Paris France
5. J. Lohstroh, E. Seevinck, and J. De Groot, "Worst-Case Static Noise Margin Criteria for Logic Circuits and their Mathematical Equivalence", IEEE J. Solid-State Circuits, vol. SC-18, NO. 6, Dec. 1983.
6. K. Anami, M. Yoshimoto, H. Shinohara, Y. Hirata, and T. Nakano, "Design Consideration of a Static Memory Cell", IEEE J. Solid-State Circuits, vol.SC-18, NO. 4, Aug. 1983.
7. E. Seevinck, F. J. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells", IEEE J. Solid-State Circuits, vol. SC-22, NO. 5, Oct. 1987.
8. O. Thomas, A. Valentian, A. Vladimirescu, and A. Amara, "An Accurate Estimation Model for Subthreshold CMOS SOI Logic", Proc. ESSCIRC, pp. 275-279, Sep 2002, Florence, Italy.
9. J. Lohstroh, "Static and dynamic noise margins of logic circuits", ", IEEE J. Solid-State Circuits, vol. SC-14, Jun. 1979.
10. B. Chappell, S.E. Schuster, G.A. Sai-Halasz, "Stability and SER Analysis of Static RAM cells", ", IEEE J. Solid-State Circuits, vol. SC-20, Feb. 1985.
11. O. Thomas, and A. Amara, "An SOI 4 Transistors Self-Refresh Ultra-Low-Voltage memory cell", ISCAS, May 2003, Thailand, Bangkok.