Stress-induced voiding beneath vias with wide copper metal leads

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volumn , Issue , 2004, Pages 103-106

  Lim, Y K ^a,b   Lim, Y H ^a   Kamat, N R ^a   See, A ^a   Lee, T J ^a   Pey, K L ^b  

^a CHARTERED SEMICONDUCTOR MANUFACTURING LTD   (Singapore)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CHAIN STRUCTURES; FLUORINATED SILICATE GLASS (FSG); INTERCONNECT TECHNOLOGY; STRESS-INDUCED VOIDS;

CHEMICAL MECHANICAL POLISHING; COPPER; DIELECTRIC MATERIALS; ELECTRIC RESISTANCE; ELECTROCHEMISTRY; ELECTROMIGRATION; ELECTROPLATING; FAILURE ANALYSIS; GLASS; GRAIN BOUNDARIES; METALLIZING; PHYSICAL VAPOR DEPOSITION; RELIABILITY; SCANNING ELECTRON MICROSCOPY; THERMAL EFFECTS;

VLSI CIRCUITS;

EID: 14844295784     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. E.T. Ogawa, J.W. McPherson, J.A. Rosal, K.J. Dickerson, T.C. Chiu, L.Y. Tsung, M.K. Jain, T.D. Bonfield, J.C. Ondrusek and W.R. McKee, "Stress-induced Voiding under Via Connected to Wide Cu Metal Leads", Proceedings of International Reliability Physics Symposium, 2002, pp.312-321.
2. B.L. Park, S.R. Hah, C.G. Park, D.K. Jeong, H.S. Son, H.S. Oh, J.H. Chung, J.L. Nam, K.M. Park and J.D. Byun, "Mechanisms of Stress-induced Voids in Multi-level Cu Interconnects", Proceedings of International Interconnect Technology Conference, 2002, pp. 130-132.
3. K. Yoshida, T. Fujimaki, K. Miyamoto, T. Honma, H. Kaneko, H. Nakazawa and M. Morita, "Stress-induced Voiding Phenomena for an Actual CMOS VLSI Interconnects", Proceedings of International Electron Device Meeting, 2002, pp.753-756.
4. T. Oshima, K. Hinode, H. Yamaguchi, H. Aoki, K. Torii, T. Saito, K. Ishikawa, J. Noguchi, M. Fukui, T. Nakamura, S. Uno, K. Tsugane, J. Murata, K. Kikushima, H. Sekisaka, E. Murakami, K. Okuyama and T. Iwasaki, "Suppression of Stress-induced Voiding in Copper Interconnects", Proceedings of International Electron Device Meeting, 2002, pp.757-760.
5. Kelvin Y.Y. Doong, Robin C.J. Wang, S.C. Lin, L.J. Hung, S.Y. Lee, C.C. Chiu, David Su, Kenneth Wu, K.L. Young and Y.K. Peng, "Stress-induced Voiding and Its Geometry Dependency Characterization", Proceedings of International Reliability Physics Symposium, 2003, pp. 156-160.
6. K. Ishikawa, T. Iwasaki, T. Fujii, N. Nakajima, M. Miyauchi, T. Ohshima, J. Noguchi, H. Aoki and T. Saito, "Impact of Metal Deposition Process upon Reliability of Dual-damascene Interconnects", Proceedings of International Interconnect Technology Conference, 2003, pp.24-26.
7. G.B. Alers, R.T. Rozbicki, G.J. Harm, S.K. Kailasam, G.W. Ray and M. Danek, "Barrier-first Integration for Improved Reliability in Copper Dual Damascene Interconnects", Proceedings of International Interconnect Technology Conference, 2003, pp.27-29.
8. Y.K. Lim, Y.H. Lim, C.S. Seet, B.C. Zhang, K.L. Chok, K.H. See, T.J. Lee, L.C. Hsia and K.L. Pey, "Stress-induced Voiding in Multi-level Copper/Low-k Interconnects", to be presented at the International Reliability Physics Symposium, 2004.