FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 52, Issue 2, 2005, Pages 350-365

  Guo, Man ^a,b   Ahmad, M Omair ^a   Swamy, M N S ^a   Wang, Chunyan ^a  

^a Dept of Electrical and Computer Engineering   (Canada)

^b 1021 Technologies   (Canada)

Author keywords

Adaptive Viterbi decoder; Field programmable gate array (FPGA) implementation; Low power design; Systolic array architecture

Indexed keywords

ADAPTIVE ALGORITHMS; COMPUTER SIMULATION; DECODING; DIGITAL ARITHMETIC; SYSTOLIC ARRAYS; TIME DIVISION MULTIPLEXING; TRELLIS CODES;

ADAPTIVE VITERBI DECODER; BINARY PHASE SHIFT KEYING; FIELD PROGRAMMABLE GATE ARRAY (FPGA) IMPLEMENTATION; LOW POWER DESIGN; SYSTOLIC ARRAY ARCHITECTURE;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 14644437710     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2004.838266     Document Type: Article

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