Low-Latency bit-Parallel systolic VLSI implementation of FIR digital filters

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 43, Issue 7, 1996, Pages 529-534

  Caraiscos, Christos G ^a   Pekmestzi, Kiamal Z ^b  

^a Technological and Educational Institute TEI of Lamia   (Greece)

^b NATIONAL TECHNICAL UNIVERSITY OF ATHENS   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; FLIP FLOP CIRCUITS; SYSTOLIC ARRAYS; VLSI CIRCUITS;

LOW LATENCY SYSTOLIC IMPLEMENTATION;

DIGITAL FILTERS;

EID: 0030194113     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.508430     Document Type: Article

References (6)

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3. P. R. Cappello and K. Steiglitz, A note on free accumulation in VLSI filter architectures, IEEE Trans. Circuits Syst., vol. 32. pp. 291-296, Mar. 1985.
4. D. Ait-Boudaoud, Unidirectional systolic multiplier, Electron. Lett., vol. 28, no. 20, pp. 1893-1894, Sept. 1992.
5. K.Z. Pekmesrzi and C. Caraiscos, Low-latency bit-parallel systolic multiplier, Electron. Lett., vol. 29, no. 4, pp. 367-369, Feb. 1993.
6. R. Roy and M. Bayoumi, An efficient two's complement systolic multiplier for real-time digital signal processing, IEEE Trans. Circuits Sys!., vol. 36, pp. 1488-1493, Nov. 1989.