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Volumn 45, Issue 5-6, 2005, Pages 869-874

Progressive breakdown in ultrathin SiON dielectrics and its effect on transistor performance

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CURRENT DENSITY; DIELECTRIC MATERIALS; ELECTRIC BREAKDOWN; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; SWITCHES; TRANSISTORS;

EID: 14644432479     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2004.10.027     Document Type: Conference Paper
Times cited : (7)

References (9)
  • 2
    • 0035416878 scopus 로고    scopus 로고
    • Two-step stress methodology for monitoring the gate oxide degradation in MOS devices
    • R. Rodríguez, E. Miranda, M. Nafría, J. Suñé, and X. Aymerich Two-step stress methodology for monitoring the gate oxide degradation in MOS devices Solid State Electron 45 2001 1317 1325
    • (2001) Solid State Electron , vol.45 , pp. 1317-1325
    • Rodríguez, R.1    Miranda, E.2    Nafría, M.3    Suñé, J.4    Aymerich, X.5
  • 7
    • 9144262565 scopus 로고    scopus 로고
    • Temperature accelerated breakdone in ultra-thin SiON dielectrics
    • R. O'Connor, G. Hughes, R. Degraeve, and B. Kaczer Temperature accelerated breakdone in ultra-thin SiON dielectrics Semicond Sci Technol 19 2004 1254 1258
    • (2004) Semicond Sci Technol , vol.19 , pp. 1254-1258
    • O'Connor, R.1    Hughes, G.2    Degraeve, R.3    Kaczer, B.4
  • 8
    • 0037972834 scopus 로고    scopus 로고
    • Collapse of MOSFET drain current after soft breakdown and its dependence on the transistor aspect ratio W/L
    • Cester A, Cimino S, Paccagnella A, Ghiaini G, Guegan G. Collapse of MOSFET drain current after soft breakdown and its dependence on the transistor aspect ratio W/L. In: Proc IRPS 2003. p. 189-95
    • Proc IRPS 2003 , pp. 189-195
    • Cester, A.1    Cimino, S.2    Paccagnella, A.3    Ghiaini, G.4    Guegan, G.5
  • 9
    • 0036540085 scopus 로고    scopus 로고
    • Analysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: A case study
    • B. Kaczer, R. Degraeve, M. Rasras, A. De Keersgieter, K. Van de Mieroop, and G. Groeseneken Analysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: a case study Microelec Rel 42 4-5 2002 555 564
    • (2002) Microelec Rel , vol.42 , Issue.4-5 , pp. 555-564
    • Kaczer, B.1    Degraeve, R.2    Rasras, M.3    De Keersgieter, A.4    Van De Mieroop, K.5    Groeseneken, G.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.