A 5Gbps CMOS LVDS transmitter with multi-phase tree-type multiplexer

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits

Volumn , Issue , 2004, Pages 228-231

  Lu, Hung Wen ^a   Su, Chau Chin ^b  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

High speed I O; Multiplexer(MUX); Serializes

Indexed keywords

BIT ERROR RATE; COMPUTER SIMULATION; DATA TRANSFER; INPUT OUTPUT PROGRAMS; MICROPROCESSOR CHIPS; MULTIPLEXING; OPTICAL DATA PROCESSING; TRANSMITTERS;

HIGH SPEED I/O; LVDS TRANSMITTERS; MULTIPLEXER (MUX); SERIALIZER;

CMOS INTEGRATED CIRCUITS;

EID: 14544304604     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. Kurisu, M.; Kaneko, M.; Suzaki, T." 2.8 Gb/s 176 mW byte-interleaved and 3.0 Gb/s 118mW bit-interleaved 8:1 multiplexers," IEEE J. of Solid-State Circuits, vol.31, No.12, Dec, 1996.
2. C.K. Yang and M.A. Horwitz, "A 0.8-um CMOS 2.5Gb/s Oversampling Receiver and Transmitter for Serial Links," IEEE J. Solid-State Circuits, Vol31, No. 12, Dec. 1996.
3. Cao, J.; Green, M.; Momtaz, A.; Vakilian, K.; Chung, D.;" OC-192 transmitter and receiver in standard 0.1 Sum CMOS," IEEE J. Solid-State Circuits, Vol. 37, No.12, Dec, 2002
4. J.G. Manteatis, "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques IEEE J. Solid-State Circuits, Vol.31, No.11, Nov, 1996.
5. Won-Hyo Lee, Jun-dong Cho, "A high speed and low power phase-frequency detector and charge-pump" IEEE Processing of the ASP-DAC, Vol. 1, 1999.
6. J. Yuan and C. Svensson, "High speed CMOS circuit technique," IEEE Journal of Solid-State Circuits, Vol. 24, Feb,1989.
7. Shi-Dai Mai, "Multi-module synchronization methodology" Master Degree dissertation of National Central University 2002