2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8 : 1 Multiplexers with a 0.15-μm CMOS technology

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 12, 1996, Pages 2024-2028

  Kurisu, Masakazu ^a,b,c,d   Kaneko, Makoto ^a,c,e   Suzaki, Tetsuyuki ^a,b,d   Tanabe, Akira ^a   Togo, Mitsuhiro ^a   Furukawa, Akio ^a   Tamura, Takao ^a   Nakajima, Ken ^a   Yoshida, Kazuyoshi ^a  

^a NEC CORPORATION   (Japan)

^b UNIVERSITY OF TSUKUBA   (Japan)

^c 4th Circuit Engineering Department

^d TOHOKU UNIVERSITY

^e Tokyo City Universtiy   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; ELECTRIC CLOCKS; MICROPROCESSOR CHIPS; OPTICAL COMMUNICATION; SHIFT REGISTERS; TIME DIVISION MULTIPLEXING;

BYTE INTERLEAVED MULTIPLEXER; STATIC SHIFT REGISTER ARCHITECTURE;

CMOS INTEGRATED CIRCUITS;

EID: 0030400847     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.545826     Document Type: Article

References (14)

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