A novel pole-zero compensation scheme using unbalanced differential pairs

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 51, Issue 2, 2004, Pages 309-318

  Ryan, Adrian P ^a   McCarthy, Oliver ^b  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b UNIVERSITY OF LIMERICK   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIFFERENTIAL AMPLIFIERS; ELECTRIC FILTERS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; POLES AND ZEROS; SENSITIVITY ANALYSIS; TRANSCONDUCTANCE;

ANALOG CIRCUITS; CONTINUOUS TIME FILTERS; LINEAR PHASE FILTERS; MULTI-TANH PRINCIPLE; POLE ZERO COMPENSATION;

MOS DEVICES;

EID: 1442361034     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2003.822409     Document Type: Article

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