A 70-mW seventh-order filter with 7-50 MHz cutoff frequency and programmable boost and group delay equalization

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 12, 1997, Pages 1987-1999

  Rezzi, Francesco ^b,c   Bietti, Ivan ^b,d   Cazzaniga, Marco ^b   Castello, Rinaldo ^a,b  

^a IEEE

^b UNIVERSITY OF PAVIA   (Italy)

^c SGS Thomson   (United States)

^d STMICROELECTRONICS   (Italy)

Author keywords

Capacitive damping; Gm C filter; HDD equalization; HDD read channel; Transconductor; Tuning circuit

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMMUNICATION CHANNELS (INFORMATION THEORY); DIGITAL TO ANALOG CONVERSION; ELECTRIC DISTORTION; EQUALIZERS; NATURAL FREQUENCIES; PULSE SHAPING CIRCUITS; SIGNAL FILTERING AND PREDICTION; TRANSCONDUCTANCE; TUNING;

CAPACITIVE DAMPING; GROUP DELAY EQUALIZATION; PARTIAL RESPONSE MAXIMUM LIKELIHOOD (PRML) READ CHANNELS; SEVENTH ORDER FILTERS; TRANSCONDUCTANCE CAPACITANCE FILTERS;

DIGITAL FILTERS;

EID: 0031359736     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.643657     Document Type: Article

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