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Volumn , Issue , 2004, Pages 372-379
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A formal verification methodology for IP-based designs
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Author keywords
[No Author keywords available]
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Indexed keywords
DIAGNOSTIC TRACES;
GLUE LOGIC;
MODEL CHECKING;
VERIFICATION METHODOLOGY;
EMBEDDED SYSTEMS;
FEEDBACK;
LARGE SCALE SYSTEMS;
MICROPROCESSOR CHIPS;
PERSONAL DIGITAL ASSISTANTS;
PRODUCT DESIGN;
SYSTEMS ANALYSIS;
NETWORK PROTOCOLS;
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EID: 13944278447
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/DSD.2004.1333299 Document Type: Conference Paper |
Times cited : (3)
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References (11)
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