Highly thermal robust NiSi for nanoscale MOSFETs utilizing a novel hydrogen plasma immersion ion implantation and Ni-Co-TiN tri-layer

IEEE Electron Device Letters

Volumn 26, Issue 2, 2005, Pages 90-92

  Yun, Jang Gn ^a   Oh, Soon Young ^a   Huang, Bin Feng ^a   Ji, Hee Hwan ^a   Kim, Yong Goo ^a   Park, Seong Hyung ^b   Lee, Heui Seung ^b   Kim, Dae Byung ^b   Kim, Ui Sik ^b   Cha, Han Seob ^b   Hu, Sang Bum ^b   Lee, Jeong Gun ^b   Baek, Sung Kweon ^c   Hwang, Hyun Sang ^c   Lee, Hi Deok ^a  

^a Chungnam National University   (South Korea)

^b MagnaChip Semiconductor Ltd   (South Korea)

^c Gwangju Institute of Science and Technology (GIST)   (South Korea)

Author keywords

Hydrogen plasma immersion ion implantation (HPIII); NanoCMOSFETs; Ni Co TiN tri layer; Ni Salicide

Indexed keywords

ANNEALING; CURRENT VOLTAGE CHARACTERISTICS; ION IMPLANTATION; LEAKAGE CURRENTS; NANOTECHNOLOGY; NICKEL COMPOUNDS; THERMODYNAMIC STABILITY; THRESHOLD VOLTAGE;

HYDROGEN PLASMA ION IMPLANTATION (HPIII); NANOCMOSFET; NANOSCALE MOSFET; NICKEL SILICIDE;

MOSFET DEVICES;

EID: 13444292422     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2004.841863     Document Type: Article

References (9)

1. H. Iwai, T. Ohguro, and S. I. Ohmi, "NiSi salicide technology for scaled CMOS," Microelectron. Eng., vol. 60, pp. 157-169, 2000.
2. J. G. Yun, H. H. Ji, S. Y. Oh, M. S. Bae, B. F. Hunag, Y. H. Park, Y. G. Kim, J. S. Wang, N. G. Sung, S. B. Hu, J. G. Lee, S. H. Park, H. S. Lee, W. J. Ho, D. B. Kim, and H. D. Lee, "Abnormal oxidation of NiSi formed on As-doped substrate," Electrochem. Solid-State Lett., vol. 7, pp. G83-G85, 2004.
3. C. J. Choi, Y. W. Ok, S. S. Hullavarad, T. Y. Seong, K. M. Lee, J. H. Lee, and Y. J. Park, "Effects of hydrogen implantation on the structural and electrical properties of nickel silicide." J. Electrochem. Soc., vol. 149, no. 9, pp. G517-G521, 2002.
4. M. Y. Wang, C. W. Wu, C. T. Lin, C. H. Hsieh, W. S. Shue, and M. S. Liang, "Novel Co-Ni bi-layer salicidation for 45 nm gate technology," in Symp. VLSI Tech. Dig., 2003, pp. 157-158.
5. M.C. Sun, M. J. Kim, J.-H. Ku, K. J. Roh, C. S. Kim, S. P. Youn, S.-W. Jung, S. Choi, N. I. Lee. H.-K. Kang, and K. P. Suh, "Thermally robust Ta-doped Ni Salicide process promising for sub-50-nm CMOSFETs," in Symp. VLSI Tech. Dig., 2003, pp. 81-82.
6. T. Ohguro, T. Morimoto, Y. Ushiku, and H. Iwai, "Analysis of anomalously large junction leakage current of nickel silicided N-type diffused layer and its improvement," in Proc. SSDM, 1993, pp. 192-194.
7. J. G. Yun, S. Y. Oh, H. H. Ji, B. F. Huang, Y. H. Park, S. H. Park, H. S. Lee, D. B. Kim, U. S. Kim, H. S. Cha, S. B. Hu, J. G. Lee, and H. D. Lee, "Optimal Ni-Co thickness extraction and two step rapid thermal process of the nickel-silicide for nanoscale complementary metal oxide semiconductor application," in Proc. Fourth Int. Workshop Junction Technol., 2004, pp. 127-130.
8. J. Lin, S. Banerjee, J. Lee, and C. Teng, "Soft breakdown in titanium-silicided shallow source/drain junctions," IEEE Electron Device Lett., vol. 11, no. 5, pp. 191-193, May 1990.
9. H.D. Lee and Y. J. Lee, "Arsenic and phosphorus double ion implanted source/drain junction for 0.25- and sub-0.25-μm MOSFET technology," IEEE Electron Device Lett., vol. 20, no. 1, pp. 42-44, Jan. 1999.