Novel Co/Ni Bi-layer Salicidation for 45nm Gate Technology

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2003, Pages 157-158

  Wang, M Y ^a   Chang, C W ^a   Wu, C M ^a   Lin, C T ^a   Hsieh, C H ^a   Shue, Winston S ^a   Liang, M S ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; GATES (TRANSISTOR); LEAKAGE CURRENTS; PLASMAS;

SALICIDATION;

SEMICONDUCTOR DEVICE MANUFACTURE;

BI-LAYER; DEVICE PERFORMANCE; GATE TECHNOLOGY; JUNCTION ISOLATION; JUNCTION LEAKAGES; NOVEL CONCEPT; PLASMA RESISTANCE; SALICIDATION; SALICIDES; STACKED FILM;

EID: 0141538304     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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2. S. Inaba, et.al., "High Performance 35nm gate length CMOS with NO oxynitride gate dielectric and Ni Salicide", IEDM Technical Digest, 2001, p641.
3. H. Iwai, T. Ohuguro and S. Ohmi, "NiSi salicide technology for scaled CMOS", Microelectronics Eng. 60 (2002) 157.
4. S. Song, et.al., "CMOS device scaling beyond 100nm", IEDM Technical Digest, 2000, p253.
5. A. Lauwers, A. Steegen, M. de-Potter, R. Lindsay, A. Satta, H. Bender, and K. Maex, "Materials aspectd, electrical performance, and scalability of Ni suicide towards sub-0.13mm technologies", J. Vac. Sci. Tech. B19 (2001) p2026.
6. Q. Xiang, B.Yu, H. Wang and M. Lin, "High performance sub-50nm CMOS with advanced gate stack", Symposium on VLSI Technology Digest of Technical Papers, 2001, p23.