Timing driven gate duplication in technology independent phase

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2001-January, Issue , 2001, Pages 577-582

  Srivastava, A ^a   Chen, Chunhong ^a   Sarrafzadeh, M ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Circuit synthesis; Circuit topology; Computer science; Delay effects; Logic; Minimization; Partitioning algorithms; Tail; Timing

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER SCIENCE; ELECTRIC NETWORK TOPOLOGY; OPTIMIZATION; SYNTHESIS (CHEMICAL);

CIRCUIT SYNTHESIS; DELAY EFFECTS; LOGIC; PARTITIONING ALGORITHMS; TAIL; TIMING;

TIMING CIRCUITS;

EID: 0003153848     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913370     Document Type: Conference Paper

References (11)

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