Scheduling of wafer test processes in semiconductor manufacturing

International Journal of Production Research

Volumn 42, Issue 2, 2004, Pages 215-242

  Ellis, K P ^a   Lu, Y ^a   Bish, E K ^a  

^a VIRGINIA POLYTECHNIC INSTITUTE AND STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER CONTROL; ELECTRONICS INDUSTRY; HEURISTIC METHODS; PROCESS ENGINEERING; SCHEDULING; SEMICONDUCTOR DEVICE TESTING; TEMPERATURE;

COMPUTER CONTROLLED TEST; SEMICONDUCTOR INDUSTRY; WAFER TEST SCHEDULING PROBLEM;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 1342287292     PISSN: 00207543     EISSN: None     Source Type: Journal    
DOI: 10.1080/0020754031000118116     Document Type: Article

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