Minimizing the total machine workload for the wafer probing scheduling problem

IIE Transactions (Institute of Industrial Engineers)

Volumn 34, Issue 2, 2002, Pages 211-220

  Pearn, W L ^a   Chung, S H ^a   Yang, M H ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

C (PROGRAMMING LANGUAGE); COMPUTER SIMULATION; INTEGER PROGRAMMING; MATHEMATICAL MODELS; PRODUCTION ENGINEERING; SCHEDULING; SILICON WAFERS;

PARALLEL MACHINE SCHEDULING PROBLEM; SOFTWARE PACKAGE CPLEX 4.0; WAFER PROBING SCHEDULING PROBLEM;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0036469072     PISSN: 0740817X     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1011952232282     Document Type: Article

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