2.44 GFLOPS 300MHz floating-point vector processing unit for high performance 3D graphics computing

European Solid-State Circuits Conference

Volumn , Issue , 1999, Pages 106-109

  Ide, Nobuhiro ^a   Hirano, Masashi ^a   Endo, Yukio ^a   Yoshioka, Shin'Ichi ^a   Murakami, Hiroaki ^a   Kunimatsu, Atsushi ^a   Sato, Toshinori ^a   Kamei, Takayuki ^a   Okada, Toyoshi ^b   Suzuoki, Masakazu ^b  

^a TOSHIBA CORPORATION   (Japan)

^b Sony Computer Entertainment Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FLOATING-POINT MULTIPLY-ACCUMULATE; HIGH-PERFORMANCE 3D GRAPHICS; MULTIPLY-ADD; PEAK PERFORMANCE; REGISTER FILES; SQUARE-ROOT OPERATIONS; VECTOR PROCESSING; VECTOR UNITS;

DIGITAL ARITHMETIC;

EID: 0343299647     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. I Ken Kutaragi, et al., "A Microprocessor with a 128b CPU, 10 Floating-point MACs, 4 Floating-point Dividers, and an MPEG2 Decorder, "Proc. of IEEE ISSCC, pp.256-257, Feb. 1999.
2. Gensoh Matsubara, et al., "30-ns 55-b Shared Radix 2 Division and Square Root Using a Self-Timed Circuit, "Proc. of 12th IEEE Symp. on Computer Arithmetic, pp.98-105, Jdy 1995.
3. John A. Kowaleski Jr., et al., "A Dual-Execution Pipelined Floating-point CMOS Processor, "Proc. of IEEE ISSCC, Feb. 1996.
4. Craig Heikes, et al., "A Dual Floating Point Coprocessor with an FMAC Architecture, " Proc. of IEEE ISSCC, Feb. 1996.
5. RKMontoye, et al., "Design of the II3M RISC Systed6000 floating-point execution unit, "IBM J. Res. Develop. Vo1.34 No.1, pp.59-70, Jan. 1990.