Repeater insertion method and its application to a 300MHz 128-bit 2-way superscalar microprocessor

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2000, Pages 641-646

  Kojima, Norman ^a   Parameswar, Yukiko ^b   Klingner, Christian ^b   Ohtaguro, Yukio ^a   Matsui, Masataka ^a   Iwasa, Shigeaki ^a   Teruyama, Tatsuo ^a   Shimazawa, Takayoshi ^a   Takeda, Hideki ^a   Hashizume, Kouji ^a   Tago, Haruyuki ^a   Yamada, Masaaki ^a  

^a TOSHIBA CORPORATION   (Japan)

^b Toshiba America Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH SPEED; INTERCONNECT DELAY; ITS APPLICATIONS; REPEATER INSERTION; SIMPLE ALGORITHM; SUPERSCALAR MICRO-PROCESSORS; TIMING PROBLEM;

COMPUTER AIDED DESIGN; MICROPROCESSOR CHIPS; VLSI CIRCUITS;

TELECOMMUNICATION REPEATERS;

EID: 84884677809     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/368434.368852     Document Type: Conference Paper

References (6)

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3. T. Okamoto, J. Cong, "Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization," Proc. IEEE Intl. Conf. on Computer-Aided Design, pp.44-49, 1996.
4. "A Microprocessor with a 128bit CPU, 10 Floating-Point MACs, 4 Floating-Point Dividers, and an MPEG2 Decoder," IEEE ISSCC Digest of Tech. Papers, Vol.42, pp.256-257, 1999.
5. "A High Bandwidth Superscalar Microprocessor for Multimedia Applications," IEEE ISSCC Digest of Tech. Papers, Vol.42, pp.258-259, 1999.
6. T. Kamei, et al., "A 300MHz Design Methodology of VU for Emotion Synthesis," Proc. ASP-DAC, to appear, 2000.