Importance of CAD tools and methodology in high speed CPU design

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2000, Pages 631-633

  Tago, Haruyuki ^a   Hashimoto, Kazuhiro ^a   Ikumi, Nobuyuki ^a   Nagamatsu, Masato ^a   Suzuoki, Masakazu ^b   Yamamoto, Yasuyuki ^b  

^a TOSHIBA CORPORATION   (Japan)

^b Sony Computer Entertainment Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN METHODOLOGY; EARLY DESIGN STAGES; EMOTION ENGINE; FORMAL VERIFICATIONS; LOAD ESTIMATION; SYSTEM EVALUATION; TIMING CLOSURES; WIRE DELAYS;

WIRE;

COMPUTER AIDED DESIGN;

EID: 84884680264     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/368434.368842     Document Type: Conference Paper

References (5)

1. Ken Kutaragi, et al., "A Microprocessor with a 128b CPU, 10 Floating-Point MACs, 4 Floating-Point Dividers, and an MPEG2 Decoder," IEEE ISSCC Digest of Technical Papers, Vol.42, pp.256-257, 1999.
2. F. Michael Raam, et al., "A High Bandwidth Superscalar Microprocessor for Multimedia Applications," IEEE ISSCC Digest of Technical Papers, Vol.42, pp.258-259, 1999.
3. T. Kamei, et al., "300MHz design methodology of VU for Emotion Synthesis," Proc. ASP-DAC, to be appeared., 2000.
4. N. Kojima, et al., "Repeater Insertion Method and its application to a 300MHz 128-bit 2-way Superscaler Microprocessor," Proc. ASP-DAC, to be appeared., 2000.
5. F. Ishihara, et al., "Clock Design of 300MHz 128-bit 2-way Superscaler Microprocessor," Proc. ASP-DAC, to be appeared., 2000.