300MHz design methodology of VU for emotion synthesis

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2000, Pages 635-640

  Kamei, Takayuki ^a   Takeda, Hideaki ^a   Ootaguro, Yukio ^a   Shimazawa, Takayoshi ^a   Tachibana, Kazuhiko ^a   Kawakami, Shin'ichi ^a   Norimatsu, Seiji ^a   Ishihara, Fujio ^a   Sato, Toshinori ^a   Murakami, Hiroaki ^a   Ide, Nobuhiro ^a   Endo, Yukio ^a   Aono, Akira ^a   Kunimatsu, Atsushi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ACCURATE ESTIMATION; DESIGN METHODOLOGY; EMOTION SYNTHESIS; FUNCTIONAL DESIGN; INTEGRATING TECHNOLOGY; OPERATING FREQUENCY; SILICON TECHNOLOGIES; STATIC TIMING ANALYSIS;

COMPUTER AIDED DESIGN; FREQUENCY ESTIMATION;

ENGINES;

EID: 84884692836     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/368434.368847     Document Type: Conference Paper

References (6)

1. K.Kutaragi, et al., "A Microprocessor with a 128b CPU, 10 Floating-Point MACs, 4 Floating-Point Dividers, and an MPEG2 Decoder," IEEE ISSCC Digest of Technical Papers, Vol.42, pp.256-257, 1999.
2. F.Michael Raam, et al., "A High Bandwidth Superscalar Microprocessor for Multimedia Applications," IEEE ISSCC Digest of Technical Papers, Vol.42, pp.258-259, 1999.
3. T.Hattori, et al., "Design Methodology of a 200MHz superscalar microprocessor SH-4," the 35th Design Automation Conference, pp.246-249, 1998.
4. A.Srinivasan and K.Chaudhary, "RITUAL:A Performance Driven Placement Algorithm for small ICs," ICCAD-91, pp.48-51, 1991.
5. C.Ramachandran, F.J.Kurdahi, D.D.Gajski, A.C.-H.Wu, and V.Chaiyukul, "Accurate Layout Area and Delay Modeling for System Level Design," ICCAD-92, pp.355-361, 1992.
6. N.Kojima, Y.Parameswar, C.Klingner, and Y.Ohtagro, "Repeater Insertion Method and its application to the 300MHz 128-bit 2-way Superscalar Microprocessor," ASP-DAC2000, in press.