An on-line CORDIC based 2-D IDCT implementation using distributed arithmetic

6th International Symposium on Signal Processing and Its Applications, ISSPA 2001 - Proceedings; 6 Tutorials in Communications, Image Processing and Signal Analysis

Volumn 1, Issue , 2001, Pages 296-299

  Yang, Yi ^a   Wang, Chunyan ^a   Omair Ahmad, M ^a   Swamy, M N S ^a  

^a Gina Cody School of Engineering and Computer Science   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DECODING; DESIGN; IMAGE PROCESSING;

COMPUTATION SPEED; DECOMPOSITION APPROACH; DISTRIBUTED ARITHMETIC; HARDWARE COMPLEXITY; INVERSE DISCRETE COSINE TRANSFORMS; ON-LINE ALGORITHMS; TWO DIMENSIONAL (2 D); VLSI ARCHITECTURES;

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EID: 3042626857     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSPA.2001.949836     Document Type: Conference Paper

References (9)

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8. F. Zhou and P. Kornerup, "High Speed DCT Using a pipelined CORDIC Algorithm," Proceedings of the 12th IEEE Symposium on Computer Arithmetic, Bath, UK, July, 1995, pp. 180-187.
9. Yung-Pin Lee, T. Chen, L. Chen, M. Chen, C. Ku, "A Cost-Effective Architecture for 8 x 8 Two-Dimensional DCT/IDCT Using Direct Method", IEEE Trans. Circuits Syst. video Tech., Vol. 7, No. 3, June 1997.