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Volumn , Issue , 2003, Pages 3-11

Architectures and algorithms for synthesizable embedded programmable logic cores

Author keywords

FPGA; Programmable logic cores; Standard cells; System on chip design

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER HARDWARE DESCRIPTION LANGUAGES; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT;

EID: 0038349193     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/611817.611820     Document Type: Conference Paper
Times cited : (27)

References (10)
  • 1
    • 0037919230 scopus 로고    scopus 로고
    • VariCore embedded programmable gate array core (EPGA) 0.18μm family
    • Actel Corp; Datasheet, December
    • Actel Corp, "VariCore Embedded Programmable Gate Array Core (EPGA) 0.18μm Family", Datasheet, December 2001.
    • (2001)
  • 2
    • 0038595374 scopus 로고    scopus 로고
    • HyperBlox FP embedded FPGA cores
    • Leopard Logic Inc; Product Brief
    • Leopard Logic Inc, "HyperBlox FP Embedded FPGA Cores", Product Brief, 2002.
    • (2002)
  • 3
    • 0037581219 scopus 로고    scopus 로고
    • M2000 FLEXEOStm configurable IP core
    • M2000, Inc
    • M2000, Inc, "M2000 FLEXEOStm Configurable IP Core", http://www.m2000.fr.
  • 4
    • 0038256789 scopus 로고    scopus 로고
    • EASIC 0.13μm core
    • eASIC
    • eASIC, "eASIC 0.13μm Core", http://www.easic.com/products/easicore013.html.
  • 6
    • 0037581213 scopus 로고    scopus 로고
    • Programmable logic array embedded in mask-programmed ASIC
    • World Intellectual Property Org. Patent #WO 01/63766 A2, Feb.
    • R. Osann, S. Eltoukhy, S. Mukund, L. Smith, "Programmable Logic Array Embedded in Mask-Programmed ASIC", World Intellectual Property Org. Patent #WO 01/63766 A2, Feb. 2001.
    • (2001)
    • Osann, R.1    Eltoukhy, S.2    Mukund, S.3    Smith, L.4
  • 8
    • 0003793410 scopus 로고    scopus 로고
    • Architecture and CAD for deep-submicron FPGAs
    • Kluwer Academic Publishers
    • V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, 1999.
    • (1999)
    • Betz, V.1    Rose, J.2    Marquardt, A.3
  • 10
    • 0032182384 scopus 로고    scopus 로고
    • Characterization and parameterized generation of synthetic combinational benchmark circuits
    • October
    • M. Hutton, J. Rose, J. Grossman, and D. Corneil, "Characterization and Parameterized Generation of Synthetic Combinational Benchmark Circuits," in IEEE Trans. on CAD, Vol. 17, No. 10, October 1998, pp. 985-996.
    • (1998) IEEE Trans. on CAD , vol.17 , Issue.10 , pp. 985-996
    • Hutton, M.1    Rose, J.2    Grossman, J.3    Corneil, D.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.