The Impact of Board Layout and Layup on PWB Warpage during fabrication and due to Reflow Solder Process: A Review of Literature

Advances in Electronic Packaging

Volumn 1, Issue , 2003, Pages 863-877

  Ahn, Wonkee ^a   Agonafer, Dereje ^a   Novotny, Shlomo ^b  

^a Woolf Hall   (United States)

^b SUN MICROSYSTEMS   (United States)

Author keywords

CTE; Layout; Layup; Printed wiring board (PWB); Printed wiring board assembly (PWBA); Thermal; Warpage

Indexed keywords

CRACKS; DELAMINATION; FABRICATION; HEAT LOSSES; PRINTED CIRCUIT BOARDS; PROBLEM SOLVING; RELIABILITY; SOLDERING ALLOYS; STRAIN; STRESS ANALYSIS; ASSEMBLY; LOADING; OPTIMIZATION; SURFACE DEFECTS;

LAYOUT; LAYUP; PRINTING WIRING BOARD ASSEMBLY (PWBA); WARPAGE; CTE; PRINTED WIRING BOARD ASSEMBLIES; PRINTED WIRING BOARDS; THERMAL; WARPAGES;

ELECTRONICS PACKAGING;

EID: 1242331966     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1115/ipack2003-35296     Document Type: Conference Paper

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