SCOPUS 정보 검색 플랫폼

VLSI Design

Volumn 12, Issue 3, 2001, Pages 399-406

On mixed PTL/static logic for low-power and high-speed circuits

(2) Cho, G R a Chen, T a

a Department of Mechanical Engineering (United States)

Author keywords

High speed; Low power; Mixed PTL Static logic; Pass transistor logic; PTL logic; VLSI

Indexed keywords

BOOLEAN FUNCTIONS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; LOGIC GATES; PERFORMANCE; VLSI CIRCUITS;

PASS TRANSISTOR LOGIC; SOFTWARE PACKAGE HSPICE;

LOGIC DESIGN;

EID: 0034927485 PISSN: 1065514X EISSN: None Source Type: Journal
DOI: 10.1155/2001/59548 Document Type: Article

Times cited : (6)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.