DLL based 10-320 MHz clock synchronizer

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2000, Pages

  Hwang, Sung Sik ^a   Joo, Ki Mo ^a   Park, Ho Jin ^a   Kim, Jae Whui ^a   Chung, Philip ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; ENERGY DISSIPATION; INTEGRATED CIRCUIT LAYOUT; SYNCHRONIZATION;

CLOCK SYNCHRONIZATION METHOD; DELAY LOCKED LOOPS (DLL);

CMOS INTEGRATED CIRCUITS;

EID: 0033726020     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2000.857415     Document Type: Conference Paper

References (7)