Scaling of lowered source/drain (LSD) and raised source/drain (RSD) ultra-thin body (UTB) SOI MOSFETs

Solid-State Electronics

Volumn 49, Issue 3, 2005, Pages 479-483

  An, Xia ^a   Huang, Ru ^a   Zhang, Xing ^a   Wang, Yangyuan ^a  

^a PEKING UNIVERSITY   (China)

Author keywords

Drain induced barrier lowering (DIBL) effect; Intrinsic delay; Lowered source drain (LSD); Parasitic capacitance; Raised source drain (RSD); Scaling; Short channel effect (SCE); Ultra thin body

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC POTENTIAL; HYDRODYNAMICS; LEAKAGE CURRENTS; LOGIC GATES; OXIDES; SEMICONDUCTING SILICON; THIN FILMS;

DRAIN-INDUCED-BARRIER-LOWERING (DIBL) EFFECTS; INTRINSIC DELAY; LOWERD SOURCE/DRAIN (LSD); PARASITIC CAPACITANCE; RAISED SOURCE/DRAIN (RSD); SCALING; SHORT-CHANNEL EFFECT (SCE); ULTRA-THIN BODY;

MOSFET DEVICES;

EID: 12344291970     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2004.11.021     Document Type: Article

References (12)

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