Notice of Removal: A 0.16-2.55-GHz CMOS active clock deskewing PLL using analog phase interpolation

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 1, 2005, Pages 110-131

  Maxim, Adrian ^a  

^a SILICON LABORATORIES   (United States)

Author keywords

Charge pump; Clock buffer; Clock deskewing; Frequency synthesizer; Phase frequency detector; Phase interpolation; Phase locked loop; Ring oscillator

Indexed keywords

CAPACITORS; COMPUTER ARCHITECTURE; ELECTRIC GENERATORS; INTERPOLATION; NATURAL FREQUENCIES; OSCILLATORS (ELECTRONIC); SPURIOUS SIGNAL NOISE; TREES (MATHEMATICS);

CHARGE PUMPS; CLOCK BUFFER; CLOCK DESKWING; FREQUENCY SYNTHESIZER; PHASE FREQUENCY DETECTOR; PHASE INTERPOLATION; PHASE-LOCKED LOOP; RING OSCILLATOR;

CMOS INTEGRATED CIRCUITS;

EID: 11944250423     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.838004     Document Type: TB

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