Efficient identification of (critical) testable path delay faults using decision diagrams

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 1, 2005, Pages 77-87

  Padmanaban, Saravanan ^a,b   Tragoudas, Spyros ^a  

^a Southern Illinois University at Carbondale   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Automatic test pattern generation (ATPG); Critical paths; Delay fault testing; Zero suppressed binary decision diagrams (ZBDDS)

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTER SIMULATION; ELECTRIC GENERATORS; GRAPH THEORY; NETWORKS (CIRCUITS); ROBUSTNESS (CONTROL SYSTEMS);

AUTOMATIC TEST PATTERN GENERATION (ATPG); CRITICAL PATHS; DELAY FAULT TESTING; ZERO-SUPPRESSED BINARY DECISION DIAGRAMS (ZBDD);

ELECTRIC FAULT CURRENTS;

EID: 11844270422     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.839488     Document Type: Conference Paper

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