메뉴 건너뛰기




Volumn , Issue , 2003, Pages 126-131

A Low Power Scheduler Using Game Theory

Author keywords

Algorithms; Auction Theory; Game Theory; High level Synthesis; Low Power Design

Indexed keywords

AUCTION THEORY; HIGH-LEVEL SYNTHESIS; LOW POWER DESIGN; LOW POWER SCHEDULER; NASH EQUILIBRIUM FUNCTION;

EID: 1142263472     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/944678.944681     Document Type: Conference Paper
Times cited : (7)

References (19)
  • 1
    • 0029182644 scopus 로고
    • Simultaneous scheduling and binding for power minimization during micro-architecture synthesis
    • A. Dasgupta and R. Karri. Simultaneous scheduling and binding for power minimization during micro-architecture synthesis. In Proc. Intl. Symp. on Low Power Electronics and Design, pp 69-74, 1995.
    • (1995) Proc. Intl. Symp. on Low Power Electronics and Design , pp. 69-74
    • Dasgupta, A.1    Karri, R.2
  • 2
    • 0031273490 scopus 로고    scopus 로고
    • SCALP: An iterative improvement based low-power data path synthesis system
    • Nov.
    • A. Raghunathan and N.K. Jha. SCALP: An iterative improvement based low-power data path synthesis system. IEEE Trans. on CAD, 16(11):1260-1277, Nov. 1997.
    • (1997) IEEE Trans. on CAD , vol.16 , Issue.11 , pp. 1260-1277
    • Raghunathan, A.1    Jha, N.K.2
  • 3
    • 0032668489 scopus 로고    scopus 로고
    • Register transfer level power optimization with emphasis on glitch analysis and reduction
    • Aug.
    • A. Raghunathan, S. Dey and N.K. Jha. Register transfer level power optimization with emphasis on glitch analysis and reduction. IEEE Trans. on CAD, 18(8):1114-1131, Aug. 1999.
    • (1999) IEEE Trans. on CAD , vol.18 , Issue.8 , pp. 1114-1131
    • Raghunathan, A.1    Dey, S.2    Jha, N.K.3
  • 5
    • 0742310646 scopus 로고    scopus 로고
    • An efficient data path synthesis algorithm for behavioral-level power optimization
    • C. Park, T. Kim and C.L. Liu. An efficient data path synthesis algorithm for behavioral-level power optimization. In Proc. Intl. Symp. on Circuits and Systems, v 1, pp 294-297, 1999.
    • (1999) Proc. Intl. Symp. on Circuits and Systems , vol.1 , pp. 294-297
    • Park, C.1    Kim, T.2    Liu, C.L.3
  • 8
    • 84888996591 scopus 로고    scopus 로고
    • Operation binding and scheduling for low power using constraint logic programming
    • F. Gruian and K. Kuchcinski. Operation binding and scheduling for low power using constraint logic programming. In Proc. Euromicro Conf., v 1, pp 83-90, 1998.
    • (1998) Proc. Euromicro Conf. , vol.1 , pp. 83-90
    • Gruian, F.1    Kuchcinski, K.2
  • 11
    • 0001730497 scopus 로고
    • Non-cooperative games
    • Sep.
    • J.F. Nash. Non-cooperative games. Annals of Mathematics, 54(2):286-295, Sep. 1951.
    • (1951) Annals of Mathematics , vol.54 , Issue.2 , pp. 286-295
    • Nash, J.F.1
  • 13
    • 0035242968 scopus 로고    scopus 로고
    • Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs
    • Feb.
    • L. Kruse, E. Schmidt, G. Jochens, A. Stammermann, A. Schulz, E. Macii and W. Nebel. Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs. IEEE Trans. on VLSI, 9(1):3-14, Feb. 2001.
    • (2001) IEEE Trans. on VLSI , vol.9 , Issue.1 , pp. 3-14
    • Kruse, L.1    Schmidt, E.2    Jochens, G.3    Stammermann, A.4    Schulz, A.5    Macii, E.6    Nebel, W.7
  • 14
    • 0023983163 scopus 로고
    • Sehwa: A software package for synthesis of pipelines from behavioral specifications
    • Mar.
    • N. Park and A.C. Parker. Sehwa: A software package for synthesis of pipelines from behavioral specifications. IEEE Trans. on CAD, 7(3):356-370, Mar. 1988.
    • (1988) IEEE Trans. on CAD , vol.7 , Issue.3 , pp. 356-370
    • Park, N.1    Parker, A.C.2
  • 17
    • 84952776604 scopus 로고    scopus 로고
    • A model checking approach to evaluating system level dynamic power management policies for embedded systems
    • S.K. Shukla and R.K. Gupta. A model checking approach to evaluating system level dynamic power management policies for embedded systems. In Proc. Intl. High-level validation and Test Workshop, pp 53-57, 2001.
    • (2001) Proc. Intl. High-level Validation and Test Workshop , pp. 53-57
    • Shukla, S.K.1    Gupta, R.K.2
  • 18
    • 0033886673 scopus 로고    scopus 로고
    • CREAM: Combined register and module assignment with floor-planning for low power data-path synthesis
    • V.K. Srikantam, N. Ranganathan and S. Srinivasan. CREAM: combined register and module assignment with floor-planning for low power data-path synthesis. In Proc. Intl. Conf. on VLSI Design, pp 228-223, 2000.
    • (2000) Proc. Intl. Conf. on VLSI Design , pp. 228-223
    • Srikantam, V.K.1    Ranganathan, N.2    Srinivasan, S.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.