CREAM: combined register and module assignment with floorplanning for low power datapath synthesis

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2000, Pages 228-233

  Srikantam, Vamsi K ^a   Ranganathan, N ^a   Srinivasan, Srikanth ^a  

^a HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; DATA FLOW ANALYSIS; ENERGY UTILIZATION; INTEGRATED CIRCUIT LAYOUT; SHIFT REGISTERS;

COMBINED REGISTER AND MODULE ASSIGNMENT; DATA FLOW GRAPH; FUNCTIONAL UNITS; HIGH LEVEL SYNTHESIS; LOW POWER DATAPATH CIRCUITS;

VLSI CIRCUITS;

EID: 0033886673     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)