Simulation of gate lag and current collapse in gallium nitride field-effect transistors

Applied Physics Letters

Volumn 85, Issue 20, 2004, Pages 4780-4782

  Braga, N ^a   Mickevicius, R ^a   Gaska, R ^b   Shur, M S ^c   Asif Khan, M ^d   Simin, G ^d  

^a Integrated Systems Inc   (United States)

^b SENSOR ELECTRONIC TECHNOLOGY INC   (United States)

^c RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^d University of South Carolina   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER LAYER; CURRENT COLLAPSE; ELECTRON LOCALIZATION; GATE LAG;

CHARGE TRANSFER; COMPUTER SIMULATION; DIFFUSION; ELECTRONS; HETEROJUNCTIONS; MOSFET DEVICES; SEMICONDUCTING GALLIUM;

FIELD EFFECT TRANSISTORS;

EID: 10944258439     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.1823018     Document Type: Article

References (7)

1. R. Ventury, N. Q. Zhang, S. Keller, and U. K. Mishra, IEEE Trans. Electron Devices 48, 560 (2001).
2. A. Koudymov, G. Simin, M. A. Khan, A. Tarakji, R. Gaska, and M. S. Shur, IEEE Electron Device Lett. 24, 680 (2003).
3. N. Pala, S. L. Rumyantsev, M. S. Shur, X. Hu, A. Tarakji, R. Gaska, M. A. Khan, G. Simin, und I. Yang, Solid-State Electron. 46, 711 (2002).
4. X. Hu, A. Koudymov, G. Simin, J. Yang, M. A. Khan, A. Tarakji, M. S. Shur, and R. Gaska, Appl. Phys. Lett. 79, 2832 (2001).
5. DESSIS ISE TCAD Manual, Release 9.5, (ISE Integrated Systems Engineering AG, Zurich, 2003).
6. N. Braga, R. Gaska, R. Mickevicius, M. S. Shur, X. Hu, M. A. Khan, G. Simin, and J. Yang, I. Appl. Phys. 95, 6409 (2004).
7. G. Simin, X. Hu, A. Tarakji, J. Zhang, A. Koudymov, S. Saygi, J. Yang, M. A. Khan, M. Shur, and R. Gaska, Jpn. J. Appl. Phys., Part 2 40, L1142 (2001).