A 15 nm ultra-thin body SOI CMOS device with double raised source/drain for 90 nm analog applications

ETRI Journal

Volumn 26, Issue 6, 2004, Pages 575-582

  Park, Chang Hyun ^a   Oh, Myung Hwan ^a   Kang, Hee Sung ^a   Kang, Ho Kyu ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

Double raised; Fully depleted SOI; Self heating; Series resistance; Si selective epitaxial growth; Single raised; Static noise margin

Indexed keywords

ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; EPITAXIAL GROWTH; OSCILLATORS (ELECTRONIC); SILICON ON INSULATOR TECHNOLOGY; SPURIOUS SIGNAL NOISE;

CHANNEL MOBILITY; CONTACT TRANSISTORS; DRAIN PROCESSES; HIGH-SPEED CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 10844293668     PISSN: 12256463     EISSN: None     Source Type: Journal    
DOI: 10.4218/etrij.04.0104.0074     Document Type: Conference Paper

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