Floating-Gate Analog Implementation of the Additive Soft-Input Soft-Output Decoding Algorithm

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 50, Issue 10, 2003, Pages 1256-1269

  Mondragón Torres, Antonio F ^a   Sánchez Sinencio, Edgar ^b   Narayanan, Krishna R ^b  

^a TEXAS INSTRUMENTS   (United States)

^b TEXAS A AND M UNIVERSITY   (United States)

Author keywords

Analog processing; Floating gate (FG) MOS transistors; Parallel concatenated convolutional codes (PCCC); Soft input soft output (SISO); Translinear circuits; Turbo codes

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; MOSFET DEVICES; TURBO CODES;

TRANSLINEAR CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 10744224501     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2003.817763     Document Type: Article

References (27)

1. S. Benedetto, D. Divsalar, G. Montorsi, and F. Pollara, "A soft-input soft-output APP module for iterative decoding of concatenated codes," IEEE Commun. Lett., vol. 1, pp. 22-24, Jan. 1997.
2. _, "Soft-input soft-output modules for the construction and distributed iterative decoding of code networks," Eur. Trans. Telecommun., vol. 9, no. 2, pp. 155-172, 1998.
3. L. Bahl, J. Cocke, F. Jelinek, and J. Raviv, "Optimal decoding of linear code for minimizing symbol error rate," IEEE Trans. Inform. Theory, vol. IT-20, pp. 284-287, Mar. 1974.
4. P. Robertson, E. Villebrun, and P. Hoeher, "A comparison of optimal and sub-optimal MAP decoding algorithms operating in the log domain," in Proc. IEEE 1995 Int. Conf. Communication 'Gateway to Globalization', vol. 2, Seattle, WA, 1995, pp. 1009-1013.
5. P. Robertson, P. Hoeher, and E. Villebrun, "Optimal and sub-optimal maximum a posteriori algorithms suitable for turbo decoding," Eur. Trans. Telecommun., vol. 8, p. 119, 1997.
6. A. F. Mondragón-Torres and E. Sánchez-Sinencio, "Floating gate analog implementation of the additive soft-input soft-output decoding algorithm," Proc. 2002 IEEE Int. Symp. Circuits and Systems, pp. 89-92, May 2002.
7. J. Hagenauer and M. Winklhofer, "The analog decoder," Proc. 1998 IEEE Int. Symp. Information Theory, p. 145, 1998.
8. P. H. Siegel, D. Divsalar, E. Eleftheriou, J. Hagenauer, D. Rowitch, and W. H. Tranter, "Guest editorial the turbo principle: From theory to practice," IEEE J. Select. Areas Commun., vol. 19, pp. 793-799, May 2001.
9. J. Hagenauer, M. Moerz, and E. Offer, "Analog turbo-networks in VLSI: The next step in turbo decoding and equalization," in Proc. Int. Symp. on Turbo Codes, Brest, France, Sept. 2000, pp. 209-218.
10. J. Hagenauer, E. Offer, C. Measson, and M. Mörz, "Decoding and equalization with analog nonlinear networks," Eur. Trans. Telecommun., vol. 10, no. 6, pp. 659-680, 1999.
11. M. Moerz, J. Hagenauer, and E. Offer, "On the analog implementation of the APP (BCJR) algorithm," in Proc. 2000 Int. Symp. Information Theory, 2000, p. 425.
12. M. Moerz, T. Gabara, R. Van, and J. Hagenauer, "An analog 0.25 μm BiCMOS tailbiting MAP decoder," in Dig. Tech. Papers ISSCC'00, 2000, pp. 356-357.
13. H.-A. Loeliger, F. Lustenberger, M. Helfenstein, and F. Tarkoy, "Probability propagation and decoding in analog VLSI," IEEE Trans. Inform. Theory, vol. 47, pp. 837-843, Feb. 2001.
14. H.-A. Loeliger, F. Tarkoy, F. Lustenberger, and M. Helfenstein, "Decoding in analog VLSI," IEEE Commun. Mag., vol. 37, pp. 99-101, Apr. 1999.
15. F. Lustenberger, M. Helfenstein, H.-A. Loeliger, F. Tarkoy, and G. Moschytz, "All-analog decoder for a binary (18, 9, 5) tail-biting trellis code," in Proc. ESSCIRC'99, Duisburg, Germany, Sept. 1999, pp. 362-365.
16. S. Benedetto and G. Montorsi, "Design of parallel concatenated convolutional codes," IEEE Trans. Commun., vol. 44, pp. 591-600, May 1996.
17. J. Hagenauer, E. Offer, and L. Papke, "Iterative decoding of binary block and convolutional codes," IEEE Trans. Inform. Theory, vol. 42, pp. 429-445, Mar. 1996.
18. B. A. Minch, C. Diorio, P. Hasler, and C. Mead, "Translinear circuits using subthreshold floating-gate MOS transistors," Analog Integr. Circuits Signal Processing, vol. 9, no. 2, pp. 167-180, 1996.
19. A. F. Mondragón-Torres, M. C. Schneider, and E. Sánchez-Sinencio, "Extraction of electrical parameters of floating-gate devices for circuit analysis, simulation and design," Proc. 2002 IEEE Midwest Symp. Circuits and Systems, pp. 311-314, Aug. 2002.
20. P. J. Black and T. H.-Y. Meng, "A unified approach to the viterbi algorithm state metric update for shift register processes," in Proc. ICASSP'92, vol. 5, 1992, pp. 629-632.
21. Y. Wu and B. D. Woerner, "Internal data width in SISO decoding module with modular renormalization," in Proc. VTC'00, vol. 1, Tokyo, Japan, 2000, pp. 675-679.
22. A. I. A. Cunha, M. C. Schneider, and C. Galup-Montoro, "An MOS transistor model for analog circuit design," IEEE J. Solid-State Circuits, vol. 33, pp. 1510-1519, Oct. 1998.
23. J. Ramirez-Angulo, G. Gonzalez-Altamirano, and S. C. Choi, "Modeling multiple-input floating-gate transistors for analog signal processing," in Proc. ISCAS'97, vol. 3, 1997, pp. 2020-2023.
24. T. Serrano-Gotarredona, B. Linares-Barranco, and A. G. Andreou, "Very wide range tunable CMOS/bipolar current mirrors with voltage clamped input," IEEE Trans. Circuits Syst. I, vol. 46, pp. 1398-1407, Nov. 1999.
25. I. E. Opris, "Analog rank extractors," IEEE Trans. Circuits Syst. I, vol. 44, pp. 1114-1121, Dec. 1997.
26. A. F. Mondragón-Torres, M. C. Schneider, and E. Sánchez-Sinencio, "Well-driven floating-gate transistors," Electron. Lett., vol. 38, pp. 530-532, 23, 2002.
27. C. J. Winstead, J. Dai, S. Little, C. J. Myers, C. Schlegel, Y.-B. Kim, and W. J. Kim, "Analog MAP decoder for (8, 4) Hamming code in subthreshold CMOS," in Proc. IEEE Int. Symp. Information Theory, 2001, p. 330.