Floating gate analog implementation of the additive soft-input soft-output decoding algorithm

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2002, Pages

  Mondragón Torres, Antonio F ^a   Sánchez Sinencio, Edgar ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; DECODING; INTEGRATED CIRCUIT LAYOUT; LINEAR INTEGRATED CIRCUITS; LOGIC GATES; PROBABILITY;

ANALOG DECODER; MULTIPLE INPUT FLOATING GATE MOS; SOFT-INPUT SOFT-OUTPUT DECODING ALGORITHM;

CMOS INTEGRATED CIRCUITS;

EID: 0036286951     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. A soft-input soft-output APP module for iterative decoding of concatenated codes
2. Soft-input soft-output modules for the construction and distributed iterative decoding of code networks
3. Optimal decoding of linear code for minimizing symbol error rate
4. Optimal and sub-optimal maximum a posteriori algorithms suitable for turbo decoding
5. The analog decoder
6. Analog turbo-networks in VLSI: The next step in turbo decoding and equalization
7. Probability propagation and decoding in analog VLSI
8. Translinear circuits using subthreshold floating-gate MOS transistors
9. An MOS transistor model for analog circuit design
10. Modeling multiple-input floating-gate transistors for analog signal processing
11. Very wide range tunable CMOS/bipolar current mirrors with voltage clamped input