Extraction of electrical parameters of floating gate devices for circuit analysis, simulation, and design

Midwest Symposium on Circuits and Systems

Volumn 1, Issue , 2002, Pages

  Mondragón Torres, Antonio F ^a   Schneider, Márcio C ^b   Sánchez Sinencio, Edgar ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

^b FEDERAL UNIVERSITY OF SANTA CATARINA   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIGITAL CIRCUITS; FLASH MEMORY; MOSFET DEVICES; TRANSISTORS;

FLOATING GATE (FG) DEVICES;

ELECTRIC NETWORK ANALYSIS;

EID: 0036976992     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. IEEE standard definitions and characterization of floating gate semiconductor arrays," IEEE Std 1005-1998, 9 Feb. 1999.
2. P. Pavan, R. Bez, P. Olivo, and E. Zanoni, "Flash memory cells- an overview," Proc. of the IEEE, vol. 85. no. 8, Aug., 1997.
3. A.I.A. Cunha, M.C. Schneider, C. Galup-Montoro, "An MOS transistor model for analog circuit design," Journal of Solid-State Circ., vol. 33, pp. 1510 1519, Oct. 1998.
4. E. Sanchez-Sinencio and A. Andreou, "Low-Voltage/Low Power Int. Circuits and Syst.," IEEE Press, Chap. 2, 1999.
5. A. Low, P. Hasler,"Cadence-based simulation of floating-gate circuits using the EKV model," 42nd Midwest Symp. on Circ. and Syst., vol. 1, pp. 141-144, 2000.
6. J. Ramirez-Angulo, G. Gonzalez-Altamirano, S.C. Choi, "Modeling multiple-input floating-gate transistors for analog signal processing," in ISCAS'97, vol. 3, pp. 2020-2023, 1997.
7. A.F. Mondragón-Torres, M.C. Schneider and E. Sanchez-Sinencio "Extraction of electrical parameters of floating gate devices for circuit analysis, simulation and design," IEEE Trans. on Circ. and Syst. II: Analog and Digital Signal Proc., subm. for publ., Dec., 2001 (available on request).