Circuit partitioning and RF isolation by through-substrate trenches

Proceedings - Electronic Components and Technology Conference

Volumn 2, Issue , 2004, Pages 1519-1523

  Sinaga, S M ^a   Polyakov, A ^a   Bartek, M ^a   Burghartz, J N ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CONDUCTIVITY; MICROPROCESSOR CHIPS; PROBLEM SOLVING; SILICON WAFERS; SWITCHING; THICKNESS MEASUREMENT;

CIRCUIT PARTITIONING; STRUCTURE DESIGN; SYSTEM ON CHIP (SOC); TRENCHES;

CROSSTALK;

EID: 10444279211     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. S. Donnay, G. Gielen, "Substrate Noise Coupling in Mixed-Signal ASICs," Kluwer Academic Publishers, Boston, 2003, pp. 47-63.
2. M. Pfost and H.M. Rein, "Modeling and Measurement of Substrate Coupling in Si-Bipolar ICs up to 40 GHz," IEEE Journal of Solid-State Circuits, Vol. 33, No. 4, 1998, pp. 52-55.
3. T. Blalack, Y. Leclercq and C. Patrick Yue, "On-Chip RF Isolation Technique," Proc. IEEE BCTM, 2002.
4. K. Joardar, "A Simple Approach to Modeling Crosstalk in Integrated Circuits," IEEE Journal of Solid-State Circuits, Vol. 29, No. 10, 1994, pp. 1212-1219.
5. C.S. Kim et al, "Deep Trench Guard Technology to Supress Coupling between Inductors in Silicon RF ICs," Microwave Symposium Digest, 2001 IEEE MTT-S International, Vol. 3, 2001.
6. D. Szmyd, L. Gambus and W. Wilbanks, "Strategies and Test Structures for Improving Isolation between Circuit Blocks," Proc. IEEE 2002 Int. Conference on Microelectrnic Test Structures, Vol. 15, 2002.
7. S. Ponnapalli et al, "Preventing a "NOISEQUAKE"," IEEE Circuit and Device Magazine, Vol. 17, Issue: 6, Nov. 2001, pp. 19-28.
8. X. Aragones, J.L. Gonzales, A. Rubio, "Analysis for Switching Noise Coupling in Mixed-Signal ICs," Kluwer Academic Publishers, Boston, 1999.
9. S.M. Sinaga et al, "On-chip Isolation in Wafer-Level Chip-Scale Packages: Substrate Thinning and Circuit Partitioning by Trenches," IMAPS 2003, 16-20 November 2003, Boston, USA, publ. IMAPS, pp. 768-773.