On-Chip Isolation in Wafer-Level Chip-Scale Packages: Substrate Thinning and Circuit Partitioning by Trenches

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5288, Issue , 2003, Pages 768-773

  Sinaga, S M ^a   Polyakov, A ^a   Bartek, M ^a   Burghartz, J N ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

Circuit partitioning; Substrate coupling; Substrate thinning; Trenching; WLCSP

Indexed keywords

CALIBRATION; COMPUTER SIMULATION; DOPING (ADDITIVES); INTEGRATED CIRCUITS; OPTIMIZATION; SEMICONDUCTING SILICON; TRENCHING;

CIRCUIT PARTIONING; SUBSTRATE COUPLING; SUBSTRATE THINNING; WAFER-LEVEL CHIP-SCALE PACKAGES (WLCSP);

CHIP SCALE PACKAGES;

EID: 2342579557     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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