Strategies and test structures for improving isolation between circuit blocks

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2002, Pages 89-93

  Szmyd, David ^a   Gambus, Laurent ^a   Wilbanks, William ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; CROSSTALK; ELECTRIC IMPEDANCE; INTEGRATED CIRCUIT TESTING; POLYSILICON; SCATTERING PARAMETERS; SEMICONDUCTOR DOPING; SILICA;

CIRCUIT BLOCKS; DEEP TRENCHES; ELECTRICAL ISOLATION; SCATTERING PARAMETER MEASUREMENTS; TEST STRUCTURES;

SEMICONDUCTOR DEVICE STRUCTURES;

EID: 0037481716     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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2. M. Pfost and H. Rein, "Modeling and Measurement of Substrate Coupling in Si-Bipolar ICs up to 40 GHz", IEEE J. Solid-State Circuits, vol. 33, no. 4, pp. 582-591, 1998.
3. K. Joardar, "Signal Isolation in BiCMOS Mixed Mode Integrated Circuits", Proc. 1995 BCTM, pp. 178-181, 1995.
4. T. Ohguro, T. Isihawa, T. Kimura, S. Samata, A. Kawasaki, T. Nagano, T. Yoshitomi, and T. Toyoshima, "High Performance Digital-Analog Mixed Devices on a Si Substrate with Resistivity beyond 1 kΩ-cm", Tech. Dig. 2000 IEDM, pp. 757-760, 2000.
5. D. Szmyd, R. Brock, N. Bell, S. Harker, G. Patrizi, J. Fraser, and R. Dondero, "QUBiC4: A Silicon RF-BiCMOS Technology for Wireless Communication ICs", Proc. 2001 BCTM pp. 60-63, 2001.
6. S. Harker, R. Havens, J. Paasschens, D. Szmyd, L. Tiemeijer, and E. Weagel, "An S-parameter Technique for Substrate Resistance Characterization of RF Bipolar Transistors", Proc. 2000 BCTM, pp. 176-179, 2000.