Parallel realization of the ATM cell header CRC

Computer Communications

Volumn 19, Issue 3 SPEC. ISS., 1996, Pages 257-263

  Ng, Seong Leong ^a   Dewar, Bill ^a  

^a UNIVERSITY OF NEW SOUTH WALES   (Australia)

Author keywords

Asynchronous Transfer Mode; Cell delineation; Cyclic redundancy checks

Indexed keywords

BIT ERROR CORRECTION; GENERATOR POLYNOMIAL; PARALLEL CYCLIC REDUNDANCY CHECK;

BINARY SEQUENCES; CIRCUIT THEORY; COMPUTER HARDWARE; COMPUTER SIMULATION; DATA PROCESSING; ERROR DETECTION; SHIFT REGISTERS;

ASYNCHRONOUS TRANSFER MODE;

EID: 0039462594     PISSN: 01403664     EISSN: None     Source Type: Journal    
DOI: 10.1016/0140-3664(96)01057-2     Document Type: Article

References (9)

1. ITU-T Recommendation I.432 B-ISDN User-Network Interface-Physical Layer Specification (03/93), 1993, pp. 16-20.
2. W.W. Peterson, Error Correcting Codes, MIT Press, 1961.
3. W.W. Peterson and D.T. Brown, Cyclic codes for error detection, in Proceedings of the IRE, January 1961, pp. 228-235.
4. A.M. Patel, A multi-channel CRC register, in AFIPS Conference Proceedings, Vol. 38, Spring 1971, pp. 11-14.
5. T.B. Pei and C. Zukowski, High-speed parallel CRC circuits in VLSI, IEEE Trans. on Comm., 40(4) (April 1992) 653-657.
6. R.J. Glaise and X. Jacquart, Fast CRC calculation, in IEEE International Conference on Computer Design, 1993, pp. 602-605.
7. R.A. Quinnell, ATM technology, EDN Asia (June 1994) 40-52.
8. SC3000 1.5-Micron Standard Cells Databook, GE/RCA Solid State (1987).
9. D.E. Dodds and L. Du, ATM framing using CRC byte, in Proceedings of ICC, 1994, pp. 410-414.