A 50 MHz CMOS pipelined majority logic decoder for (1057, 813) difference-set cyclic code

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E79-A, Issue 7, 1996, Pages 1060-1066

  Kobayashi, Kazumasa ^a   Yamano, Kouji ^a   Kokubun, Hidcki ^a   Kobayashit, Kiichi ^a  

^a NHK SCIENCE AND TECHNICAL RESEARCH LABORATORIES   (Japan)

Author keywords

(1057, 813) code; Difference set cyclic codes; Majority logic decoding; Pipelining

Indexed keywords

ALGORITHMS; CODES (SYMBOLS); DIGITAL COMMUNICATION SYSTEMS; FORMAL LOGIC; PERFORMANCE; PIPELINE CODES;

DIFFERENCE-SET CYCLIC CODES; MAJORITY LOGIC DECODING; PIPELINING;

DECODING;

EID: 0030195741     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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