Fast configurable polynomial division for error control coding applications

Proceedings - 7th International On-Line Testing Workshop, IOLTW 2001

Volumn 2001-January, Issue , 2001, Pages 158-161

  Monteiro, Fabrice ^a   Dandache, Abbas ^a   Lepley, Bernard ^a  

^a UNIVERSITÉ DE LORRAINE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ERRORS; PIPELINES;

DATA RATES; DATA TRANSMISSION RATES; ERROR CONTROL CODING; ERROR-CORRECTING; PIPELINE STRUCTURE; POLYNOMIAL DIVISIONS; SPEED PERFORMANCE; SYNTHESIS STAGES;

POLYNOMIALS;

EID: 33645131155     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2001.937836     Document Type: Conference Paper

References (6)

1. T-B. Pei, C. Zukowski, "High-Speed Parallel CRC Circuits in VLSI", IEEE Transactions on Communications, vol. 40, no. 4, april 1992.
2. T.K. Matsushima, T. Matsushima, S. Hirasawa, "Parallel Encoder and Decoder Architecture for Cyclic Codes", IEICE Transactions Fundamentals, vol. E79-A, no. 9, septembre 1996.
3. F. Elguibaly, "A Fast Parallel Multiplier-Accumulator Using the Modified Booth Algorithm", IEEE Transaction on Circuits and Systems II, vol. 47, no. 9, septembre 2000.
4. ∗8 bit multiplier in CMOS technology", IEEE Transactions on VLSI Systems, vol. 3, no. 1, 1995.
5. F. Monteiro, S. Philip, A. Dandache, B. Lepley, "A New Processor Architecture Dedicated to Digital Modem Applications", IEEE International Symposium on Circuits And Systems, Monterey (California), may 1998.
6. T. Vallino, S. Piestrak, A. Dandache, F. Monteiro, B. Lepley, "Study of a New Parallel Architecture Dedicated to the Family of the DSCC Code", 5th IEEE International On-Line Testing Workshop, Rhodos (Greece), July 1999.