Multi-level pass-transistor logic for low-power ULSIs

IEEE Symposium on Low Power Electronics

Volumn , Issue , 1995, Pages 14-15

  Sasaki, Yasuhiko ^a   Yano, Kazuo ^a   Yamashita, Shunzo ^a   Chikata, Hidetoshi ^a   Rikino, Kunihito ^a   Uchiyama, Kunio ^a   Seki, Koichi ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; OPTIMIZATION; ULSI CIRCUITS;

BINARY DECISION DIAGRAM; BOOLEAN MANIPULATION; CMOS FACTORIZATION TECHNIQUE; MULTI-LEVEL PASS TRANSISTOR LOGIC; SINGLE-LEVEL PASS-TRANSISTOR LOGIC;

LOGIC CIRCUITS;

EID: 0029532072     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)