Hybrid dynamic/quadratic programming algorithm for interconnect tree optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 5, 2001, Pages 680-686

  Mo, Yu Yen ^a,b   Chu, Chris ^a  

^a Iowa State University   (United States)

^b SUN MICROSYSTEMS   (United States)

Author keywords

Buffer insertion; Interconnect; Optimization; Performance optimization; Physical design; Timing optimization

Indexed keywords

ALGORITHMS; BUFFER CIRCUITS; DELAY CIRCUITS; DYNAMIC PROGRAMMING; GATES (TRANSISTOR); MATHEMATICAL MODELS; QUADRATIC PROGRAMMING;

BUFFER INSERTION;

INTEGRATED CIRCUITS;

EID: 0035333423     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.920705     Document Type: Article

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